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author | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 14:21:22 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 14:21:22 -0700 |
commit | 53817b85753deb3dc5647414de67de1373798049 (patch) | |
tree | 7d46afa0000187b7fccbe1a446f8cb6593921aee /passes/pmgen/xilinx_dsp.pmg | |
parent | d122083a112d51ba0d91e44c37b1d4d9d11080aa (diff) | |
download | yosys-53817b85753deb3dc5647414de67de1373798049.tar.gz yosys-53817b85753deb3dc5647414de67de1373798049.tar.bz2 yosys-53817b85753deb3dc5647414de67de1373798049.zip |
Use new port/param overload in pmg
Diffstat (limited to 'passes/pmgen/xilinx_dsp.pmg')
-rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 7d34c6a78..bb29bdd99 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -42,7 +42,7 @@ code sigA sigB sigC sigD sigM sigD = dsp->connections_.at(\D, SigSpec()); SigSpec P = port(dsp, \P); - if (dsp->parameters.at(\USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") { + if (param(dsp, \USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") { // Only care about those bits that are used int i; for (i = 0; i < GetSize(P); i++) { @@ -79,8 +79,8 @@ endcode match preAdd if sigD.empty() || sigD.is_fully_zero() // Ensure that preAdder not already used - if dsp->parameters.at(\USE_DPORT, Const("FALSE")).decode_string() == "FALSE" - if dsp->connections_.at(\INMODE, Const(0, 5)).is_fully_zero() + if param(dsp, \USE_DPORT, Const("FALSE")).decode_string() == "FALSE" + if port(dsp, \INMODE, Const(0, 5)).is_fully_zero() select preAdd->type.in($add) // Output has to be 25 bits or less @@ -348,7 +348,7 @@ endcode match overflow if ffP - if dsp->parameters.at(\USE_PATTERN_DETECT, Const("NO_PATDET")).decode_string() == "NO_PATDET" + if param(dsp, \USE_PATTERN_DETECT, Const("NO_PATDET")).decode_string() == "NO_PATDET" select overflow->type.in($ge) select GetSize(port(overflow, \Y)) <= 48 select port(overflow, \B).is_fully_const() |