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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 13:33:27 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 22:31:04 -0700 |
| commit | 52583ecff82eb9dc78e10b7bfd33c1be3d4dcc67 (patch) | |
| tree | a98f181452bff75b614e226ad69db10bdabc17ef /passes/pmgen/xilinx_dsp.pmg | |
| parent | 6d689726193db4d46f7618ff00707e4f30366ad5 (diff) | |
| download | yosys-52583ecff82eb9dc78e10b7bfd33c1be3d4dcc67.tar.gz yosys-52583ecff82eb9dc78e10b7bfd33c1be3d4dcc67.tar.bz2 yosys-52583ecff82eb9dc78e10b7bfd33c1be3d4dcc67.zip | |
Revert "Fix TODOs"
This reverts commit 8674a6c68d563908014d16671567459499c6dc99.
Diffstat (limited to 'passes/pmgen/xilinx_dsp.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 3523db3a4..8a2c2caf5 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -103,6 +103,11 @@ code sigA sigB sigC sigD sigM clock } else sigM = P; + // TODO: Check if necessary + // This sigM could have no users if downstream $add + // is narrower than $mul result, for example + if (sigM.empty()) + reject; clock = port(dsp, \CLK, SigBit()); endcode @@ -154,6 +159,16 @@ match preAdd optional endmatch +code sigA sigD + // TODO: Check if this is necessary? + if (preAdd) { + sigA = port(preAdd, \A); + sigD = port(preAdd, \B); + if (GetSize(sigA) < GetSize(sigD)) + std::swap(sigA, sigD); + } +endcode + // (4) If pre-adder was present, find match 'A' input for A2REG // If pre-adder was not present, move ADREG to A2REG // Then match 'A' input for A1REG |