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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-09 16:07:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-09 16:07:40 -0700 |
| commit | 1df9c5d277aa70d4dc1088d0030a756f342bb8fb (patch) | |
| tree | 5f737129d684fbbf219342735657418c79c22963 /passes/pmgen/xilinx_dsp.pmg | |
| parent | 5f8f0e13833ef052adb4d2d3deb8e965734127fd (diff) | |
| download | yosys-1df9c5d277aa70d4dc1088d0030a756f342bb8fb.tar.gz yosys-1df9c5d277aa70d4dc1088d0030a756f342bb8fb.tar.bz2 yosys-1df9c5d277aa70d4dc1088d0030a756f342bb8fb.zip | |
Oops
Diffstat (limited to 'passes/pmgen/xilinx_dsp.pmg')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index afbd6ef81..f01eeb245 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -411,8 +411,7 @@ code dffQ if (port(ff, \CLK) != clock) reject; } - else - dffclock = port(ff, \CLK); + dffclock = port(ff, \CLK); dff = ff; dffD = dffQ; |