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| author | Clifford Wolf <clifford@clifford.at> | 2019-01-13 10:57:11 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-01-15 11:23:25 +0100 |
| commit | b9545aa0e1260f3d7123ec63e9dcfb0e022e2ff3 (patch) | |
| tree | 91b4f2d03eca96ecfd9d1403781e904a24631e99 /passes/pmgen/ice40_dsp.pmg | |
| parent | ad69c668cedaab76f84c982411d7cddbd868cccf (diff) | |
| download | yosys-b9545aa0e1260f3d7123ec63e9dcfb0e022e2ff3.tar.gz yosys-b9545aa0e1260f3d7123ec63e9dcfb0e022e2ff3.tar.bz2 yosys-b9545aa0e1260f3d7123ec63e9dcfb0e022e2ff3.zip | |
Progress in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/pmgen/ice40_dsp.pmg')
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 5a0af3e04..2b9bb8783 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -1,6 +1,6 @@ -state SigBit clock -state bool clock_pol, clock_vld -state SigSpec sigA, sigB, sigY +state <SigBit> clock +state <bool> clock_pol clock_vld +state <SigSpec> sigA sigB sigY match mul select mul->type.in($mul) @@ -10,7 +10,8 @@ endmatch match ffA select ffA->type.in($dff) - filter port(ffA, \Q) === port(mul, \A) + select nusers(port(ffA, \Q)) == 2 + filter <SigSpec> port(ffA, \Q) === port(mul, \A) optional endmatch @@ -28,11 +29,12 @@ endcode match ffB select ffB->type.in($dff) - filter port(ffB, \Q) === port(mul, \B) + select nusers(port(ffA, \Q)) == 2 + filter <SigSpec> port(ffB, \Q) === port(mul, \B) optional endmatch -code sigB clock clok_pol clock_vld +code sigB clock clock_pol clock_vld sigB = port(mul, \B); if (ffB != nullptr) { @@ -51,11 +53,12 @@ endcode match ffY select ffY->type.in($dff) - filter port(ffY, \D) === port(mul, \Y) + select nusers(port(ffY, \D)) == 2 + filter <SigSpec> port(ffY, \D) === port(mul, \Y) optional endmatch -code sigY clock clok_pol clock_vld +code sigY clock clock_pol clock_vld sigY = port(mul, \Y); if (ffY != nullptr) { |