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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 22:39:47 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 22:39:47 -0700 |
| commit | a59f80834f7f8ecf02ed0c608dce1a237a874d34 (patch) | |
| tree | 3ac85141fe3c0c262867c1550373048a36d5fa89 /passes/pmgen/ice40_dsp.pmg | |
| parent | 4100825b810408e25b1773cb1e57d25821f164b5 (diff) | |
| download | yosys-a59f80834f7f8ecf02ed0c608dce1a237a874d34.tar.gz yosys-a59f80834f7f8ecf02ed0c608dce1a237a874d34.tar.bz2 yosys-a59f80834f7f8ecf02ed0c608dce1a237a874d34.zip | |
SB_MAC16 ffCD to not pack same as ffO
Diffstat (limited to 'passes/pmgen/ice40_dsp.pmg')
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 35db22807..09fd8406d 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -188,7 +188,7 @@ match add select nusers(port(add, AB)) == 2 index <SigBit> port(add, AB)[0] === sigH[0] filter GetSize(port(add, AB)) <= GetSize(sigH) - filter port(add, AB) == sigH.extract(0, GetSize(port(add, AB))) + filter port(add, AB) == sigH.extract(0, GetSize(port(add, AB))) filter nusers(sigH.extract_end(GetSize(port(add, AB)))) <= 1 set addAB AB optional @@ -280,7 +280,7 @@ code argD ffO ffOholdmux ffOrstmux ffOholdpol ffOrstpol sigO sigCD clock clock_p endcode code argQ ffCD ffCDholdmux ffCDholdpol ffCDrstpol sigCD clock clock_pol - if (!sigCD.empty() && + if (!sigCD.empty() && sigCD != sigO && (mul->type != \SB_MAC16 || (!param(mul, \C_REG).as_bool() && !param(mul, \D_REG).as_bool()))) { argQ = sigCD; subpattern(in_dffe); |