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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-22 13:01:49 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-22 13:01:49 -0700 |
| commit | 5a14b6e1f6331d7587d566173e0d82e0c6c77f4c (patch) | |
| tree | c8d4c2d5a8c3484d414e279176f032ab4b8ac765 /passes/pmgen/ice40_dsp.pmg | |
| parent | 3a7aeb028d7680a73c18ec700939cca76aab0433 (diff) | |
| download | yosys-5a14b6e1f6331d7587d566173e0d82e0c6c77f4c.tar.gz yosys-5a14b6e1f6331d7587d566173e0d82e0c6c77f4c.tar.bz2 yosys-5a14b6e1f6331d7587d566173e0d82e0c6c77f4c.zip | |
Pack adders not just accumulators
Diffstat (limited to 'passes/pmgen/ice40_dsp.pmg')
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index e4c6238c5..a92cf8dd4 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -1,7 +1,7 @@ pattern ice40_dsp state <SigBit> clock -state <bool> clock_pol +state <bool> clock_pol sigS_signed state <SigSpec> sigA sigB sigY sigS state <Cell*> addAB muxAB @@ -92,14 +92,16 @@ match addB optional endmatch -code addAB sigS +code addAB sigS sigS_signed if (addA) { addAB = addA; - sigS = port(addA, \B); + sigS = port(addAB, \B); + sigS_signed = param(addAB, \B_SIGNED).as_bool(); } if (addB) { addAB = addB; - sigS = port(addB, \A); + sigS = port(addAB, \A); + sigS_signed = param(addAB, \A_SIGNED).as_bool(); } if (addAB) { int natural_mul_width = GetSize(sigA) + GetSize(sigB); @@ -144,6 +146,7 @@ match ffS select nusers(port(ffS, \D)) == 2 index <SigSpec> port(ffS, \D) === port(muxAB, \Y) index <SigSpec> port(ffS, \Q) === sigS + optional endmatch code clock clock_pol |