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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-09 17:23:12 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-09 17:23:12 -0700 |
| commit | 3dd3ab98c2bb83f644fb1962d4de27a7416b0113 (patch) | |
| tree | 3c51c7c1de3073330c6d29aa31c8873a5bd3c072 /passes/pmgen/ice40_dsp.pmg | |
| parent | 6d254f2de802ccd71b6514b0f5e4c0b44c415ae4 (diff) | |
| download | yosys-3dd3ab98c2bb83f644fb1962d4de27a7416b0113.tar.gz yosys-3dd3ab98c2bb83f644fb1962d4de27a7416b0113.tar.bz2 yosys-3dd3ab98c2bb83f644fb1962d4de27a7416b0113.zip | |
Improve ice40_dsp for non-fully-32-bit adders
Diffstat (limited to 'passes/pmgen/ice40_dsp.pmg')
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index e0a213e85..c59c5d20a 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -106,7 +106,9 @@ endcode match addA select addA->type.in($add) select nusers(port(addA, \A)) == 2 - index <SigSpec> port(addA, \A) === sigH + filter param(addA, \A_WIDTH).as_int() <= GetSize(sigH) + //index <SigSpec> port(addA, \A) === sigH.extract(0, param(addA, \A_WIDTH).as_int()) + filter port(addA, \A) == sigH.extract(0, param(addA, \A_WIDTH).as_int()) optional endmatch @@ -114,7 +116,9 @@ match addB if !addA select addB->type.in($add, $sub) select nusers(port(addB, \B)) == 2 - index <SigSpec> port(addB, \B) === sigH + filter param(addB, \B_WIDTH).as_int() <= GetSize(sigH) + //index <SigSpec> port(addB, \B) === sigH.extract(0, param(addB, \B_WIDTH).as_int()) + filter port(addB, \B) == sigH.extract(0, param(addB, \B_WIDTH).as_int()) optional endmatch @@ -144,7 +148,8 @@ code addAB sigCD sigO if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width)) reject; - if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool())) + // If accumulator, check adder width and signedness + if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool())) reject; sigO = port(addAB, \Y); |