Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing

1 files changed, 68 insertions, 31 deletions

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 8b1ac2563..1a62c7bda 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -2,18 +2,27 @@ pattern ice40_dsp
 
 state <SigBit> clock
 state <bool> clock_pol
-state <SigSpec> sigA sigB sigCD sigH sigO
+state <SigSpec> sigA sigB sigCD sigH sigO sigOused
 state <Cell*> addAB muxAB
 
 match mul
-	select mul->type.in($mul, $__MUL16X16)
+	select mul->type.in($mul, \SB_MAC16)
 	select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
-	select GetSize(mul->getPort(\Y)) > 10
 endmatch
 
+code sigH
+	if (mul->type == $mul)
+		sigH = mul->getPort(\Y);
+	else if (mul->type == \SB_MAC16)
+		sigH = mul->getPort(\O);
+	else log_abort();
+	if (GetSize(sigH) <= 10)
+		reject;
+endcode
+
 match ffA
-			    // TODO: Support $dffe too by checking if all enable signals are identical
 	select ffA->type.in($dff)
+	filter mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
 	filter !port(mul, \A).remove_const().empty()
 	filter includes(port(ffA, \Q).to_sigbit_set(), port(mul, \A).remove_const().to_sigbit_set())
 	optional
@@ -23,9 +32,9 @@ code sigA clock clock_pol
 	sigA = port(mul, \A);
 
 	if (ffA) {
-        for (auto b : port(ffA, \Q))
-            if (b.wire->get_bool_attribute(\keep))
-                reject;
+		for (auto b : port(ffA, \Q))
+			if (b.wire->get_bool_attribute(\keep))
+				reject;
 
 		clock = port(ffA, \CLK).as_bit();
 		clock_pol = param(ffA, \CLK_POLARITY).as_bool();
@@ -36,6 +45,7 @@ endcode
 
 match ffB
 	select ffB->type.in($dff)
+	filter mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
 	filter !port(mul, \B).remove_const().empty()
 	filter includes(port(ffB, \Q).to_sigbit_set(), port(mul, \B).remove_const().to_sigbit_set())
 	optional
@@ -45,9 +55,9 @@ code sigB clock clock_pol
 	sigB = port(mul, \B);
 
 	if (ffB) {
-        for (auto b : port(ffB, \Q))
-            if (b.wire->get_bool_attribute(\keep))
-                reject;
+		for (auto b : port(ffB, \Q))
+			if (b.wire->get_bool_attribute(\keep))
+				reject;
 
 		SigBit c = port(ffB, \CLK).as_bit();
 		bool cp = param(ffB, \CLK_POLARITY).as_bool();
@@ -65,19 +75,20 @@ endcode
 match ffH
 	select ffH->type.in($dff)
 	select nusers(port(ffH, \D)) == 2
-	index <SigSpec> port(ffH, \D) === port(mul, \Y)
+	index <SigSpec> port(ffH, \D) === sigH
+	// Ensure pipeline register is not already used
+	filter mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
 	optional
 endmatch
 
 code sigH sigO clock clock_pol
-	sigH = port(mul, \Y);
 	sigO = sigH;
 
 	if (ffH) {
 		sigH = port(ffH, \Q);
-        for (auto b : sigH)
-            if (b.wire->get_bool_attribute(\keep))
-                reject;
+		for (auto b : sigH)
+			if (b.wire->get_bool_attribute(\keep))
+				reject;
 
 		sigO = sigH;
 
@@ -119,6 +130,13 @@ code addAB sigCD sigO
                 sigCD.extend_u0(32, param(addAB, \A_SIGNED).as_bool());
 	}
 	if (addAB) {
+		if (mul->type == \SB_MAC16) {
+			// Ensure that adder is not used
+			if (param(mul, \TOPOUTPUT_SELECT).as_int() != 3 ||
+					param(mul, \BOTOUTPUT_SELECT).as_int() != 3)
+				reject;
+		}
+
 		int natural_mul_width = GetSize(sigA) + GetSize(sigB);
 		int actual_mul_width = GetSize(sigH);
 		int actual_acc_width = GetSize(sigO);
@@ -154,28 +172,49 @@ code muxAB
 		muxAB = muxB;
 endcode
 
+// Extract the bits of P that actually have a consumer
+// (as opposed to being a dummy)
+code sigOused
+	for (int i = 0; i < GetSize(sigO); i++)
+		if (!sigO[i].wire || nusers(sigO[i]) == 1)
+			sigOused.append(State::Sx);
+		else
+			sigOused.append(sigO[i]);
+endcode
+
 match ffO_lo
 	select ffO_lo->type.in($dff)
-	filter GetSize(sigO) >= param(ffO_lo, \WIDTH).as_int()
-	filter nusers(sigO.extract(0,param(ffO_lo, \WIDTH).as_int())) == 2
-	filter includes(port(ffO_lo, \D).to_sigbit_set(), sigO.extract(0,param(ffO_lo, \WIDTH).as_int()).to_sigbit_set())
+	filter nusers(sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()))) == 2
+	filter includes(port(ffO_lo, \D).to_sigbit_set(), sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int())).remove_const().to_sigbit_set())
 	optional
 endmatch
 
 match ffO_hi
 	select ffO_hi->type.in($dff)
-	filter GetSize(sigO) >= 16+param(ffO_hi, \WIDTH).as_int()
-	filter nusers(sigO.extract(16,param(ffO_hi, \WIDTH).as_int())) == 2
-	filter includes(port(ffO_hi, \D).to_sigbit_set(), sigO.extract(16,param(ffO_hi, \WIDTH).as_int()).to_sigbit_set())
+	filter GetSize(sigOused) > 16
+	filter nusers(sigOused.extract_end(16)) == 2
+	filter includes(port(ffO_hi, \D).to_sigbit_set(), sigOused.extract_end(16).remove_const().to_sigbit_set())
 	optional
 endmatch
 
 code clock clock_pol sigO sigCD
 	if (ffO_lo || ffO_hi) {
+		if (mul->type == \SB_MAC16) {
+			// Ensure that register is not already used
+			if (param(mul, \TOPOUTPUT_SELECT).as_int() == 1 ||
+					param(mul, \BOTOUTPUT_SELECT).as_int() == 1)
+				reject;
+
+			// Ensure that OLOADTOP/OLOADBOT is unused or zero
+			if ((mul->hasPort(\OLOADTOP) && !port(mul, \OLOADTOP).is_fully_zero())
+				|| (mul->hasPort(\OLOADBOT) && !port(mul, \OLOADBOT).is_fully_zero()))
+				reject;
+		}
+
 		if (ffO_lo) {
-            for (auto b : port(ffO_lo, \Q))
-                if (b.wire->get_bool_attribute(\keep))
-                    reject;
+			for (auto b : port(ffO_lo, \Q))
+				if (b.wire->get_bool_attribute(\keep))
+					reject;
 
 			SigBit c = port(ffO_lo, \CLK).as_bit();
 			bool cp = param(ffO_lo, \CLK_POLARITY).as_bool();
@@ -186,14 +225,13 @@ code clock clock_pol sigO sigCD
 			clock = c;
 			clock_pol = cp;
 
-			if (port(ffO_lo, \Q) != sigO.extract(0,param(ffO_lo, \WIDTH).as_int()))
-				sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
+			sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
 		}
 
 		if (ffO_hi) {
-            for (auto b : port(ffO_hi, \Q))
-                if (b.wire->get_bool_attribute(\keep))
-                    reject;
+			for (auto b : port(ffO_hi, \Q))
+				if (b.wire->get_bool_attribute(\keep))
+					reject;
 
 			SigBit c = port(ffO_hi, \CLK).as_bit();
 			bool cp = param(ffO_hi, \CLK_POLARITY).as_bool();
@@ -204,8 +242,7 @@ code clock clock_pol sigO sigCD
 			clock = c;
 			clock_pol = cp;
 
-			if (port(ffO_hi, \Q) != sigO.extract(16,param(ffO_hi, \WIDTH).as_int()))
-				sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
+			sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
 		}
 
 		// Loading value into output register is not