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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 15:00:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 15:00:40 -0700 |
| commit | 2983a35dc058a5f5a1ab7b23cc55dd6f83667d88 (patch) | |
| tree | b3339de6f016af73504979e14e6d7f4d5b9c5c76 /passes/pmgen/ice40_dsp.pmg | |
| parent | 7df0e77565ea9dc46d0eeca536d1be47851326e5 (diff) | |
| download | yosys-2983a35dc058a5f5a1ab7b23cc55dd6f83667d88.tar.gz yosys-2983a35dc058a5f5a1ab7b23cc55dd6f83667d88.tar.bz2 yosys-2983a35dc058a5f5a1ab7b23cc55dd6f83667d88.zip | |
Update comment
Diffstat (limited to 'passes/pmgen/ice40_dsp.pmg')
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 24bdfd3f2..8221cdb69 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -89,11 +89,11 @@ code sigB clock clock_pol endcode match ffFJKG + // Ensure pipeline register is not already used if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool()) select ffFJKG->type.in($dff) select nusers(port(ffFJKG, \D)) == 2 index <SigSpec> port(ffFJKG, \D) === sigH - // Ensure pipeline register is not already used optional endmatch |