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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 10:57:32 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 10:57:32 -0700 |
| commit | 9ad11ea2cc25f764bcd4e27dfc12c0f8041cb48a (patch) | |
| tree | 67adaf365846a143a6acbcccd767bb56ff253447 /passes/pmgen/ice40_dsp.cc | |
| parent | 8f0e796be131c2a47694e786ff901cc9970917c6 (diff) | |
| download | yosys-9ad11ea2cc25f764bcd4e27dfc12c0f8041cb48a.tar.gz yosys-9ad11ea2cc25f764bcd4e27dfc12c0f8041cb48a.tar.bz2 yosys-9ad11ea2cc25f764bcd4e27dfc12c0f8041cb48a.zip | |
Fine tune ice40_dsp.pmg, add support for packing subsets of registers
Diffstat (limited to 'passes/pmgen/ice40_dsp.cc')
| -rw-r--r-- | passes/pmgen/ice40_dsp.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index 963a7d7a1..f6a701540 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -23,13 +23,16 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +template<class T> bool includes(const T &lhs, const T &rhs) { + return std::includes(lhs.begin(), lhs.end(), rhs.begin(), rhs.end()); +} #include "passes/pmgen/ice40_dsp_pm.h" void create_ice40_dsp(ice40_dsp_pm &pm) { auto &st = pm.st_ice40_dsp; -#if 0 +#if 1 log("\n"); log("ffA: %s\n", log_id(st.ffA, "--")); log("ffB: %s\n", log_id(st.ffB, "--")); @@ -100,7 +103,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) cell->setPort("\\IRSTTOP", State::S0); cell->setPort("\\IRSTBOT", State::S0); - if (st.clock_vld) + if (st.clock != SigBit()) { cell->setPort("\\CLK", st.clock); cell->setPort("\\CE", State::S1); |