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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-05 14:08:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-05 14:08:14 -0700 |
| commit | feb2ddb52bd7ca590596e22f73a5d3c153907391 (patch) | |
| tree | ac399f601c409dbccada7fe4fb29bd276af131f5 /passes/opt | |
| parent | a3a80b755cb78866060f71348e2a0b14f96c574b (diff) | |
| download | yosys-feb2ddb52bd7ca590596e22f73a5d3c153907391.tar.gz yosys-feb2ddb52bd7ca590596e22f73a5d3c153907391.tar.bz2 yosys-feb2ddb52bd7ca590596e22f73a5d3c153907391.zip | |
Fix typo in opt_rmdff
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 2abffa2a9..eeb992a3e 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -292,8 +292,8 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) sig_q = dff->getPort("\\Q"); sig_c = dff->getPort("\\C"); sig_e = dff->getPort("\\E"); - val_cp = RTLIL::Const(dff->type[6] == 'P', 1); - val_ep = RTLIL::Const(dff->type[7] == 'P', 1); + val_cp = RTLIL::Const(dff->type[7] == 'P', 1); + val_ep = RTLIL::Const(dff->type[8] == 'P', 1); } else if (dff->type == "$ff") { sig_d = dff->getPort("\\D"); |