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author | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 12:50:21 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 12:50:21 -0700 |
commit | fc0e36d1c02c22a578020aa1f2c90c86844fefe6 (patch) | |
tree | bb7deb8d1d091b9869462c1d4d32868d429f2d70 /passes/opt | |
parent | 4e9b1d36fa896a8280e9c4295cf9a4e2a084f927 (diff) | |
download | yosys-fc0e36d1c02c22a578020aa1f2c90c86844fefe6.tar.gz yosys-fc0e36d1c02c22a578020aa1f2c90c86844fefe6.tar.bz2 yosys-fc0e36d1c02c22a578020aa1f2c90c86844fefe6.zip |
wreduce for $sub
Diffstat (limited to 'passes/opt')
-rw-r--r-- | passes/opt/wreduce.cc | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 1fbc41082..e8c2cb726 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -365,6 +365,29 @@ struct WreduceWorker } } + if (cell->type.in("$add", "$sub")) { + SigSpec A = cell->getPort("\\A"); + SigSpec B = cell->getPort("\\B"); + bool sub = cell->type == "$sub"; + + int i; + for (i = 0; i < GetSize(sig); i++) { + if (B[i] != S0 && (sub || A[i] != S0)) + break; + if (B[i] == S0) + module->connect(sig[i], A[i]); + else if (A[i] == S0) + module->connect(sig[i], B[i]); + else log_abort(); + } + if (i > 0) { + cell->setPort("\\A", A.extract(i, -1)); + cell->setPort("\\B", B.extract(i, -1)); + sig.remove(0, i); + bits_removed += i; + } + } + if (GetSize(sig) == 0) { log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); module->remove(cell); |