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| author | Clifford Wolf <clifford@clifford.at> | 2018-02-26 11:46:05 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-02-26 11:46:05 +0100 |
| commit | fba499b8666ef33bc5b11ce2df7b8b18a5aeaa75 (patch) | |
| tree | 298def7d6af880f90e23f4f66c0dc379bbd3278c /passes/opt | |
| parent | 0d636964b81ed5db4a7031a24c4b04e3bc879ad5 (diff) | |
| download | yosys-fba499b8666ef33bc5b11ce2df7b8b18a5aeaa75.tar.gz yosys-fba499b8666ef33bc5b11ce2df7b8b18a5aeaa75.tar.bz2 yosys-fba499b8666ef33bc5b11ce2df7b8b18a5aeaa75.zip | |
Fix opt_rmdff handling of $dlatchsr
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index edec42c4d..b5edb357b 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -154,6 +154,9 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) if (used_pol_set && used_pol_clr && pol_set != pol_clr) return did_something; + if (cell->type == "$dlatchsr") + return did_something; + State unified_pol = used_pol_set ? pol_set : pol_clr; if (cell->type == "$dffsr") |