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authorClifford Wolf <clifford@clifford.at>2019-03-14 20:35:15 +0100
committerClifford Wolf <clifford@clifford.at>2019-03-14 20:52:00 +0100
commitf806b95ed6a2f2c1a0e5c8884676fd384e510143 (patch)
treed19c96dd742baaf9e5b936758f2cdf582cd796ac /passes/opt
parent44a44a06ed0a7489d6d3500c5fddc4a122afffa0 (diff)
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Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/opt')
-rw-r--r--passes/opt/opt_expr.cc7
1 files changed, 7 insertions, 0 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 26a3ca7bc..a05db2a4f 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -155,6 +155,13 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
new_b.append_bit(it.first.second);
}
+ if (cell->type.in("$and", "$or") && i == GRP_CONST_A) {
+ log(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a));
+ module->connect(new_y, new_b);
+ module->connect(new_conn);
+ continue;
+ }
+
RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
c->setPort("\\A", new_a);