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| author | Clifford Wolf <clifford@clifford.at> | 2013-02-27 16:27:20 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-02-27 16:27:20 +0100 |
| commit | f28b6aff40a65aa30a04b77cd51e6c0a346e739e (patch) | |
| tree | 918542380d8baa1ef7484cd481ec67f6c4496acf /passes/opt | |
| parent | c59d77aa30d81a248063181ec8e3f746c2aec1c3 (diff) | |
| download | yosys-f28b6aff40a65aa30a04b77cd51e6c0a346e739e.tar.gz yosys-f28b6aff40a65aa30a04b77cd51e6c0a346e739e.tar.bz2 yosys-f28b6aff40a65aa30a04b77cd51e6c0a346e739e.zip | |
Implemented basic functionality of "extract" pass
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_rmunused.cc | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/passes/opt/opt_rmunused.cc b/passes/opt/opt_rmunused.cc index 29a6f2bc4..33c09f287 100644 --- a/passes/opt/opt_rmunused.cc +++ b/passes/opt/opt_rmunused.cc @@ -141,6 +141,16 @@ static void rmunused_module_signals(RTLIL::Module *module) used_signals_nodrivers.add(it2.second); } } + for (auto &it : module->wires) { + RTLIL::Wire *wire = it.second; + if (wire->port_id > 0) { + RTLIL::SigSpec sig = RTLIL::SigSpec(wire); + assign_map.apply(sig); + used_signals.add(sig); + if (!wire->port_input) + used_signals_nodrivers.add(sig); + } + } std::vector<RTLIL::Wire*> del_wires; for (auto &it : module->wires) { |