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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-19 16:33:54 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-19 16:33:54 -0700 |
| commit | ee5995641ebd7ff0d933213370c1d0dd4e7787e0 (patch) | |
| tree | 6387a445c149215b02a782db29ce313ad18e7ff8 /passes/opt | |
| parent | a0cc795e85541b0326b6d4396a726142f0d0f8bb (diff) | |
| download | yosys-ee5995641ebd7ff0d933213370c1d0dd4e7787e0.tar.gz yosys-ee5995641ebd7ff0d933213370c1d0dd4e7787e0.tar.bz2 yosys-ee5995641ebd7ff0d933213370c1d0dd4e7787e0.zip | |
opt_expr: optimise 1-bit $xor or $_XOR_ with constant input
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_expr.cc | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 4a2f170b8..e4daf6fe6 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -496,6 +496,19 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } + if (cell->type == ID($_XOR_) || (cell->type == ID($xor) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID(A_SIGNED)).as_bool())) + { + SigBit sig_a = assign_map(cell->getPort(ID::A)); + SigBit sig_b = assign_map(cell->getPort(ID::B)); + if (!sig_a.wire) + std::swap(sig_a, sig_b); + if (sig_b == State::S0 || sig_b == State::S1) { + cover("opt.opt_expr.xor_buffer"); + replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a); + goto next_cell; + } + } + if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor), ID($neg)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1) { @@ -1590,7 +1603,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } int const_bit_set = get_highest_hot_index(const_sig); - if(const_bit_set >= var_width) + if (const_bit_set >= var_width) { string cmp_name; if (cmp_type == ID($lt) || cmp_type == ID($le)) |