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| author | Alyssa Milburn <amilburn@zall.org> | 2019-12-15 20:40:38 +0100 |
|---|---|---|
| committer | Alyssa Milburn <amilburn@zall.org> | 2019-12-15 20:40:38 +0100 |
| commit | e709fd3da1c7e3ae36ee43a997fbd413909c764e (patch) | |
| tree | 8da08b4701f074386af283885ea3214c5e033222 /passes/opt | |
| parent | 52875b0d61b2b1cc83a9e9d51964a92027c3758c (diff) | |
| download | yosys-e709fd3da1c7e3ae36ee43a997fbd413909c764e.tar.gz yosys-e709fd3da1c7e3ae36ee43a997fbd413909c764e.tar.bz2 yosys-e709fd3da1c7e3ae36ee43a997fbd413909c764e.zip | |
Fix opt_expr.eqneq.cmpzero debug print
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_expr.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 6cf66fb95..4a2f170b8 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -978,7 +978,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons { cover_list("opt.opt_expr.eqneq.cmpzero", "$eq", "$ne", cell->type.str()); log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell), - log_id(module), "$eq" ? "$logic_not" : "$reduce_bool"); + log_id(module), cell->type == ID($eq) ? "$logic_not" : "$reduce_bool"); cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool); if (assign_map(cell->getPort(ID::A)).is_fully_zero()) { cell->setPort(ID::A, cell->getPort(ID::B)); |