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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 11:11:50 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 11:11:50 -0700 |
| commit | e6d5147214bd157c457654dc46547775ec6ad324 (patch) | |
| tree | 420b4e76aec5d70e2f83b2aa56a783ea5b461a66 /passes/opt | |
| parent | 0c78c62d6c043925293c0ff934c41f2df6932b85 (diff) | |
| parent | 5545cd3c108ef240ccf6278b2734412acf81cd2a (diff) | |
| download | yosys-e6d5147214bd157c457654dc46547775ec6ad324.tar.gz yosys-e6d5147214bd157c457654dc46547775ec6ad324.tar.bz2 yosys-e6d5147214bd157c457654dc46547775ec6ad324.zip | |
Merge remote-tracking branch 'origin/master' into eddie/cleanup
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_expr.cc | 25 | ||||
| -rw-r--r-- | passes/opt/wreduce.cc | 6 |
2 files changed, 28 insertions, 3 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index ef4b8b57a..b2dc9a448 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -640,6 +640,31 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons did_something = true; } } + + if (cell->type.in("$add", "$sub")) { + RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); + RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); + bool sub = cell->type == "$sub"; + + int i; + for (i = 0; i < GetSize(sig_y); i++) { + if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx) + module->connect(sig_y[i], sig_a[i]); + else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx) + module->connect(sig_y[i], sig_b[i]); + else + break; + } + if (i > 0) { + cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str()); + cell->setPort("\\A", sig_a.extract_end(i)); + cell->setPort("\\B", sig_b.extract_end(i)); + cell->setPort("\\Y", sig_y.extract_end(i)); + cell->fixup_parameters(); + did_something = true; + } + } } if (cell->type.in("$reduce_xor", "$reduce_xnor", "$shift", "$shiftx", "$shl", "$shr", "$sshl", "$sshr", diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 1fbc41082..1eeca2748 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -342,9 +342,9 @@ struct WreduceWorker } } - if (cell->type.in("$pos", "$add", "$mul", "$and", "$or", "$xor")) + if (cell->type.in("$pos", "$add", "$mul", "$and", "$or", "$xor", "$sub")) { - bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); + bool is_signed = cell->getParam("\\A_SIGNED").as_bool() || cell->type == "$sub"; int a_size = 0, b_size = 0; if (cell->hasPort("\\A")) a_size = GetSize(cell->getPort("\\A")); @@ -352,7 +352,7 @@ struct WreduceWorker int max_y_size = max(a_size, b_size); - if (cell->type == "$add") + if (cell->type.in("$add", "$sub")) max_y_size++; if (cell->type == "$mul") |