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| author | Clifford Wolf <clifford@clifford.at> | 2017-02-09 16:06:58 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-02-09 16:06:58 +0100 |
| commit | e6cc67b46f637e5fc971c79e8f115c225b807120 (patch) | |
| tree | 09d4bec9091ac3fd1976db3065ef1e26726a0fae /passes/opt | |
| parent | 848062088cfc702ba2f4616e1091f63c636bbe5b (diff) | |
| download | yosys-e6cc67b46f637e5fc971c79e8f115c225b807120.tar.gz yosys-e6cc67b46f637e5fc971c79e8f115c225b807120.tar.bz2 yosys-e6cc67b46f637e5fc971c79e8f115c225b807120.zip | |
Fix handling of init attributes with strange width
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_merge.cc | 8 | ||||
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 4 |
2 files changed, 9 insertions, 3 deletions
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 97989d271..07e4dd39f 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -280,8 +280,12 @@ struct OptMergeWorker dff_init_map.set(module); for (auto &it : module->wires_) - if (it.second->attributes.count("\\init") != 0) - dff_init_map.add(it.second, it.second->attributes.at("\\init")); + if (it.second->attributes.count("\\init") != 0) { + Const initval = it.second->attributes.at("\\init"); + for (int i = 0; i < GetSize(initval) && i < GetSize(it.second); i++) + if (initval[i] == State::S0 || initval[i] == State::S1) + dff_init_map.add(SigBit(it.second, i), initval[i]); + } bool did_something = true; while (did_something) diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 00094738c..0eefd6a86 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -244,7 +244,9 @@ struct OptRmdffPass : public Pass { { if (wire->attributes.count("\\init") != 0) { Const initval = wire->attributes.at("\\init"); - dff_init_map.add(wire, initval); + for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) + if (initval[i] == State::S0 || initval[i] == State::S1) + dff_init_map.add(SigBit(wire, i), initval[i]); for (int i = 0; i < GetSize(wire); i++) { SigBit wire_bit(wire, i), mapped_bit = assign_map(wire_bit); if (mapped_bit.wire) { |