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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-20 12:32:00 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-20 12:32:00 -0800 |
| commit | d038cea3c7c5dd9f147c4da0e44de0e664df089f (patch) | |
| tree | 90cec90ac65ce2257ec8fea2a2d640da101dc7a6 /passes/opt | |
| parent | 83d36394f86510abf944ada407d4a1f4d7eefcd0 (diff) | |
| download | yosys-d038cea3c7c5dd9f147c4da0e44de0e664df089f.tar.gz yosys-d038cea3c7c5dd9f147c4da0e44de0e664df089f.tar.bz2 yosys-d038cea3c7c5dd9f147c4da0e44de0e664df089f.zip | |
More stringent check for flop cells
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_merge.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 643cf0215..8dd238bc7 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -222,7 +222,8 @@ struct OptMergeWorker return true; } - if (cell1->type.begins_with("$") && conn1.count(ID(Q)) != 0) { + if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") || cell1->type.in("$adff", "$sr", "$ff") || + cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH"))) { std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector(); std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector(); for (size_t i = 0; i < q1.size(); i++) @@ -324,7 +325,8 @@ struct OptMergeWorker module->connect(RTLIL::SigSig(it.second, other_sig)); assign_map.add(it.second, other_sig); - if (cell->type.begins_with("$") && it.first == ID(Q)) { + if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") || cell->type.in("$adff", "$sr", "$ff") || + cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH"))) { for (auto c : it.second.chunks()) { auto jt = c.wire->attributes.find(ID(init)); if (jt == c.wire->attributes.end()) |