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author | Johann Glaser <Johann.Glaser@gmx.at> | 2013-03-17 22:02:30 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-03-18 07:28:31 +0100 |
commit | cd8008bda01091b7da63d4a2c7b2fe3749ee9f36 (patch) | |
tree | 8da22fcbe26dcad0c0babcba07a965ef0623233b /passes/opt | |
parent | ba3793b6420f2a0288c43be0cd4016fd5473acaf (diff) | |
download | yosys-cd8008bda01091b7da63d4a2c7b2fe3749ee9f36.tar.gz yosys-cd8008bda01091b7da63d4a2c7b2fe3749ee9f36.tar.bz2 yosys-cd8008bda01091b7da63d4a2c7b2fe3749ee9f36.zip |
fixed typos
Diffstat (limited to 'passes/opt')
-rw-r--r-- | passes/opt/opt_muxtree.cc | 2 | ||||
-rw-r--r-- | passes/opt/opt_rmunused.cc | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 5602b5eea..49b72f15b 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -406,7 +406,7 @@ struct OptMuxtreePass : public Pass { log(" opt_muxtree [selection]\n"); log("\n"); log("This pass analyzes the control signals for the multiplexer trees in the design\n"); - log("and identifies inputs that can never be active. In then removes this dead\n"); + log("and identifies inputs that can never be active. It then removes this dead\n"); log("branches from the multiplexer trees.\n"); log("\n"); log("This pass only operates on completely selected modules without processes.\n"); diff --git a/passes/opt/opt_rmunused.cc b/passes/opt/opt_rmunused.cc index c72a45876..6cec9b294 100644 --- a/passes/opt/opt_rmunused.cc +++ b/passes/opt/opt_rmunused.cc @@ -242,9 +242,9 @@ struct OptRmUnusedPass : public Pass { log(" opt_rmunused [selection]\n"); log("\n"); log("This pass identifies wires and cells that are unused and removes them. Other\n"); - log("often remove cells but leave the wires in the design or reconnect the wires\n"); - log("but leave the old cells in the design. This pass can be used to clean up after\n"); - log("the passes that do the actual work.\n"); + log("passes often remove cells but leave the wires in the design or reconnect the\n"); + log("wires but leave the old cells in the design. This pass can be used to clean up\n"); + log("after the passes that do the actual work.\n"); log("\n"); log("This pass only operates on completely selected modules without processes.\n"); log("\n"); |