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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-19 13:32:04 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-19 13:32:04 +0100 |
| commit | b7fcf1fb9a7a6b4f84357d61bc4bb3c711511c7d (patch) | |
| tree | 34f2e90d97b9411425c64a68d920c460e8caa543 /passes/opt | |
| parent | 1d30c66a7f97cd522a87893c64ebe3a933f6b0ba (diff) | |
| download | yosys-b7fcf1fb9a7a6b4f84357d61bc4bb3c711511c7d.tar.gz yosys-b7fcf1fb9a7a6b4f84357d61bc4bb3c711511c7d.tar.bz2 yosys-b7fcf1fb9a7a6b4f84357d61bc4bb3c711511c7d.zip | |
keep $mux and $_MUX_ optimizations separate in opt_const
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_const.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 5b87aeaa2..1e9b1331b 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -113,7 +113,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module) if (input.match("0 ")) ACTION_DO("\\Y", input.extract(0, 1)); } - if (cell->type == "$_MUX_" ||(cell->type == "$mux" && cell->parameters["\\WIDTH"].as_int() == 1)) { + if (cell->type == "$_MUX_") { RTLIL::SigSpec input; input.append(cell->connections["\\S"]); input.append(cell->connections["\\B"]); @@ -128,8 +128,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module) // TODO: "10 " -> replace with "!S" gate // TODO: "0 " -> replace with "B AND S" gate // TODO: " 1 " -> replace with "A OR S" gate - // TODO: "1 " -> replace with "B OR !S" gate - // TODO: " 0 " -> replace with "A AND !S" gate + // TODO: "1 " -> replace with "B OR !S" gate (?) + // TODO: " 0 " -> replace with "A AND !S" gate (?) if (input.match(" *")) ACTION_DO_Y(x); #endif } |