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| author | Clifford Wolf <clifford@clifford.at> | 2015-09-01 12:51:23 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-09-01 12:51:23 +0200 |
| commit | b10ea0550dadfdc352447115c214e02c6e5663da (patch) | |
| tree | 8b1d2e82f7edb0dbb1a0b7ba90e48ce3088c1f4e /passes/opt | |
| parent | 522176c946b25557e754a3067fe2465e0d6df26c (diff) | |
| download | yosys-b10ea0550dadfdc352447115c214e02c6e5663da.tar.gz yosys-b10ea0550dadfdc352447115c214e02c6e5663da.tar.bz2 yosys-b10ea0550dadfdc352447115c214e02c6e5663da.zip | |
gcc-4.6 build fixes
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/wreduce.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 70a40e960..dfcfebf4b 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -348,9 +348,9 @@ struct WreducePass : public Pass { continue; for (auto c : module->selected_cells()) - if (c->type.in({"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool", + if (c->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool", "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt", - "$logic_not", "$logic_and", "$logic_or"}) && GetSize(c->getPort("\\Y")) > 1) { + "$logic_not", "$logic_and", "$logic_or") && GetSize(c->getPort("\\Y")) > 1) { SigSpec sig = c->getPort("\\Y"); c->setPort("\\Y", sig[0]); c->setParam("\\Y_WIDTH", 1); |