diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-07-10 12:52:29 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-07-10 12:52:29 +0200 |
| commit | a9fefc6ce1c0c351f88e61ec2a01ec64fc30d28f (patch) | |
| tree | 45cb94a5406e5a5030f2f24db373072a65b7f8c8 /passes/opt | |
| parent | ed62fcdbe224207434c5f643734f2627264826c5 (diff) | |
| download | yosys-a9fefc6ce1c0c351f88e61ec2a01ec64fc30d28f.tar.gz yosys-a9fefc6ce1c0c351f88e61ec2a01ec64fc30d28f.tar.bz2 yosys-a9fefc6ce1c0c351f88e61ec2a01ec64fc30d28f.zip | |
Bugfixes for empty signal vectors
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_const.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 4223ebe3b..34d0f9244 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -217,6 +217,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons assign_map.apply(a); \ if (a.is_fully_const()) { \ a.optimize(); \ + if (a.chunks.empty()) a.chunks.push_back(RTLIL::SigChunk()); \ RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \ RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks[0].data, dummy_arg, \ cell->parameters["\\A_SIGNED"].as_bool(), false, \ @@ -232,6 +233,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons assign_map.apply(a), assign_map.apply(b); \ if (a.is_fully_const() && b.is_fully_const()) { \ a.optimize(), b.optimize(); \ + if (a.chunks.empty()) a.chunks.push_back(RTLIL::SigChunk()); \ + if (b.chunks.empty()) b.chunks.push_back(RTLIL::SigChunk()); \ RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks[0].data, b.chunks[0].data, \ cell->parameters["\\A_SIGNED"].as_bool(), \ cell->parameters["\\B_SIGNED"].as_bool(), \ |