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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-09 10:32:12 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-09 10:32:12 -0700 |
commit | 9f1b82f5941778a3691ce0ef08e0d06547451110 (patch) | |
tree | b80e1f7e891c4689e175c679c2f9d9624612004a /passes/opt | |
parent | 8350dfb80906742068b8ee771d15f0741624fed0 (diff) | |
download | yosys-9f1b82f5941778a3691ce0ef08e0d06547451110.tar.gz yosys-9f1b82f5941778a3691ce0ef08e0d06547451110.tar.bz2 yosys-9f1b82f5941778a3691ce0ef08e0d06547451110.zip |
opt_expr -fine to trim LSBs of $alu too
Diffstat (limited to 'passes/opt')
-rw-r--r-- | passes/opt/opt_expr.cc | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index acdc39937..5a82b7066 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -642,26 +642,31 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if (cell->type.in("$add", "$sub")) { + if (cell->type.in("$add", "$sub", "$alu")) + { RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); RTLIL::SigSpec sig_y = cell->getPort("\\Y"); - bool sub = cell->type == "$sub"; + bool ignore_a = cell->type == "$sub" || (cell->type == "$alu" && !cell->getPort("\\BI").is_fully_zero()); int i; for (i = 0; i < GetSize(sig_y); i++) { if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx) module->connect(sig_y[i], sig_a[i]); - else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx) + else if (!ignore_a && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx) module->connect(sig_y[i], sig_b[i]); else break; } if (i > 0) { - cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str()); + cover_list("opt.opt_expr.fine", "$add", "$sub", "$alu", cell->type.str()); cell->setPort("\\A", sig_a.extract_end(i)); cell->setPort("\\B", sig_b.extract_end(i)); cell->setPort("\\Y", sig_y.extract_end(i)); + if (cell->type == "$alu") { + cell->setPort("\\X", cell->getPort("\\X").extract_end(i)); + cell->setPort("\\CO", cell->getPort("\\CO").extract_end(i)); + } cell->fixup_parameters(); did_something = true; } |