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authorEddie Hung <eddie@fpgeh.com>2019-06-06 12:46:42 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-06 12:46:42 -0700
commit978fda94f684185a7d583a3865b7a68459344e46 (patch)
tree942ab4ef407456ab39bf02627bd90fe769fd7e45 /passes/opt
parentd2172c6846f710e9a362708e3308dd302110deb2 (diff)
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Fix spacing
Diffstat (limited to 'passes/opt')
-rw-r--r--passes/opt/muxpack.cc11
1 files changed, 5 insertions, 6 deletions
diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index 963083107..cb13a45b0 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -43,9 +43,8 @@ struct MuxpackWorker
for (auto wire : module->wires())
{
if (wire->port_output || wire->get_bool_attribute("\\keep")) {
- for (auto bit : sigmap(wire)) {
+ for (auto bit : sigmap(wire))
sigbit_with_non_chain_users.insert(bit);
- }
}
}
@@ -58,8 +57,8 @@ struct MuxpackWorker
SigSpec y_sig = sigmap(cell->getPort("\\Y"));
if (sig_chain_next.count(a_sig))
- for (auto a_bit : a_sig.bits())
- sigbit_with_non_chain_users.insert(a_bit);
+ for (auto a_bit : a_sig.bits())
+ sigbit_with_non_chain_users.insert(a_bit);
else
sig_chain_next[a_sig] = cell;
@@ -70,7 +69,7 @@ struct MuxpackWorker
sig_chain_next[b_sig] = cell;
sig_chain_prev[y_sig] = cell;
- continue;
+ continue;
}
for (auto conn : cell->connections())
@@ -182,7 +181,7 @@ struct MuxpackWorker
first_cell->setPort("\\B", b_sig);
first_cell->setPort("\\S", s_sig);
- first_cell->setParam("\\S_WIDTH", GetSize(s_sig));
+ first_cell->setParam("\\S_WIDTH", GetSize(s_sig));
first_cell->setPort("\\Y", last_cell->getPort("\\Y"));
cursor += cases;