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| author | Clifford Wolf <clifford@clifford.at> | 2013-10-16 16:16:06 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-16 16:16:06 +0200 |
| commit | 96e7abad48c942452f247267f219d38be902f804 (patch) | |
| tree | cddc562437bc3c44376a34b2245d7bee12cc8816 /passes/opt | |
| parent | b6db2d9b3382ac3725f81586198ad7d9c014e990 (diff) | |
| download | yosys-96e7abad48c942452f247267f219d38be902f804.tar.gz yosys-96e7abad48c942452f247267f219d38be902f804.tar.bz2 yosys-96e7abad48c942452f247267f219d38be902f804.zip | |
Added iopadmap pass
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_clean.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 96c4c7a18..2ea60c03c 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -47,7 +47,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) wire2driver.insert(sig, cell); } } - if (cell->type == "$memwr") + if (cell->type == "$memwr" || cell->attributes.count("\\keep")) queue.insert(cell); unused.insert(cell); } |