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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 08:43:44 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 08:43:44 -0700 |
| commit | 9245f0d3f564644290b6650b3f8f642789062e9e (patch) | |
| tree | 9fb6c404057fe328e2d00857cc6707bbc5ee9e8b /passes/opt | |
| parent | 6f971470f83b8e4ed29232be4b6cb5da89d50dc0 (diff) | |
| download | yosys-9245f0d3f564644290b6650b3f8f642789062e9e.tar.gz yosys-9245f0d3f564644290b6650b3f8f642789062e9e.tar.bz2 yosys-9245f0d3f564644290b6650b3f8f642789062e9e.zip | |
Copy-paste typo
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_expr.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 73f48317a..00d7d6063 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -758,7 +758,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } if (width < GetSize(sig_a)) { - cover_list("opt.opt_expr.xbit", "$shiftx", "$shift", cell->type.str()); + cover_list("opt.opt_expr.trim", "$shiftx", "$shift", cell->type.str()); sig_a.remove(width, GetSize(sig_a)-width); cell->setPort(ID::A, sig_a); cell->setParam(ID(A_WIDTH), width); |