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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-19 14:34:27 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-19 14:34:27 -0700 |
| commit | 8d1fa0e3b91c9439d2ab1e24c29b7ccdfcc91606 (patch) | |
| tree | f4fb54b414e301d3e3f3c4897f3f4e11209d7b22 /passes/opt | |
| parent | 213a8955898282163d237944e2eef12e9e0e3e24 (diff) | |
| download | yosys-8d1fa0e3b91c9439d2ab1e24c29b7ccdfcc91606.tar.gz yosys-8d1fa0e3b91c9439d2ab1e24c29b7ccdfcc91606.tar.bz2 yosys-8d1fa0e3b91c9439d2ab1e24c29b7ccdfcc91606.zip | |
opt_expr: remove redundant
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_expr.cc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index c818fefc5..723830aa0 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -682,9 +682,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigSpec sig_y = cell->getPort(ID::Y); RTLIL::SigSpec sig_co = cell->getPort(ID(CO)); - if (sig_ci.wire || sig_bi.wire) - goto next_cell; - bool sub = (sig_ci == State::S1 && sig_bi == State::S1); // If not a subtraction, yet there is a carry or B is inverted |