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| author | whitequark <whitequark@whitequark.org> | 2018-12-07 17:13:52 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2018-12-07 17:13:52 +0000 |
| commit | 7ec740b7ad4ee4bc02e2564671e0153cdd08152f (patch) | |
| tree | 1509de1bf1e0413a23f48aaf066a69ea9068cb8f /passes/opt | |
| parent | 9eb03d458dcb2a3ba91a84739e764558b26e335c (diff) | |
| download | yosys-7ec740b7ad4ee4bc02e2564671e0153cdd08152f.tar.gz yosys-7ec740b7ad4ee4bc02e2564671e0153cdd08152f.tar.bz2 yosys-7ec740b7ad4ee4bc02e2564671e0153cdd08152f.zip | |
opt_lut: leave intact LUTs with cascade feeding module outputs.
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_lut.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 4207fbdb9..ba2cc6ee7 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -225,6 +225,12 @@ struct OptLutWorker log("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB)); + if (index.query_is_output(lutA->getPort("\\Y"))) + { + log(" Not combining LUTs (cascade connection feeds module output).\n"); + continue; + } + pool<SigBit> lutA_inputs; pool<SigBit> lutB_inputs; for (auto &bit : lutA_input) |