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| author | Clifford Wolf <clifford@clifford.at> | 2013-12-27 14:21:24 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-27 14:21:24 +0100 |
| commit | 7b02a44efbb81ce2c97dcb87f1d8ca016c14ba76 (patch) | |
| tree | c961f054ee7fcb71ea1bbc2dd12a7447676536b4 /passes/opt | |
| parent | 369bf81a7049c96f62af084bb5007fbf45e36ab4 (diff) | |
| download | yosys-7b02a44efbb81ce2c97dcb87f1d8ca016c14ba76.tar.gz yosys-7b02a44efbb81ce2c97dcb87f1d8ca016c14ba76.tar.bz2 yosys-7b02a44efbb81ce2c97dcb87f1d8ca016c14ba76.zip | |
Fixed/improved opt_const $eq/$ne/$eqx/$nex handling
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_const.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 30d85588c..d84910ee1 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -166,6 +166,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (b.chunks[i].wire == NULL && b.chunks[i].data.bits[0] > RTLIL::State::S1) continue; } + if (a.chunks[i] == b.chunks[i]) + continue; new_a.append(a.chunks[i]); new_b.append(b.chunks[i]); } @@ -177,7 +179,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons goto next_cell; } - if (new_a.width != a.width) { + if (new_a.width < a.width || new_b.width < b.width) { new_a.optimize(); new_b.optimize(); cell->connections["\\A"] = new_a; |