diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 11:25:42 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 11:25:42 -0700 |
| commit | 6cd8cace0c1d2a9f7b1f1cd56a223c38a5ea799a (patch) | |
| tree | 0c41cbe0ee18d5af63e5d8ff4736d85e1c642fb5 /passes/opt | |
| parent | 847c54088e14c141560a9f627f5aea5da5bf4517 (diff) | |
| download | yosys-6cd8cace0c1d2a9f7b1f1cd56a223c38a5ea799a.tar.gz yosys-6cd8cace0c1d2a9f7b1f1cd56a223c38a5ea799a.tar.bz2 yosys-6cd8cace0c1d2a9f7b1f1cd56a223c38a5ea799a.zip | |
Fix
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_expr.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 330c56e22..6dea611e3 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -506,7 +506,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons did_something = true; } else { cover("opt.opt_expr.unary_buffer"); - replace_cell(assign_map, module, cell, "unary_buffer", "\\Y", cell->getPort(ID(A))); + replace_cell(assign_map, module, cell, "unary_buffer", ID(Y), cell->getPort(ID(A))); } goto next_cell; } @@ -747,7 +747,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && cell->getPort(ID(Y)).size() == 1 && invert_map.count(assign_map(cell->getPort(ID(A)))) != 0) { cover_list("opt.opt_expr.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str()); - replace_cell(assign_map, module, cell, "double_invert", ID(Y), invert_map.at(assign_map(cell->getPort(ID("A"))))); + replace_cell(assign_map, module, cell, "double_invert", ID(Y), invert_map.at(assign_map(cell->getPort(ID(A))))); goto next_cell; } |