diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-09-18 11:55:31 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-09-18 11:55:31 +0200 |
| commit | 51e1295d79f373133bd48ace30a76add0d294f02 (patch) | |
| tree | 0239141c8424d2de0a53de4c574eb967ca85718e /passes/opt | |
| parent | b7535a6c750108697161a72b5f2fe0001d0dd375 (diff) | |
| download | yosys-51e1295d79f373133bd48ace30a76add0d294f02.tar.gz yosys-51e1295d79f373133bd48ace30a76add0d294f02.tar.bz2 yosys-51e1295d79f373133bd48ace30a76add0d294f02.zip | |
Added detection of "mux inverter" chains in opt_const
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_const.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 32a804260..6295b8881 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -249,6 +249,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if ((cell->type == "$_NOT_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\A").size() == 1 && cell->getPort("\\Y").size() == 1) invert_map[assign_map(cell->getPort("\\Y"))] = assign_map(cell->getPort("\\A")); + if ((cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == SigSpec(State::S1) && cell->getPort("\\B") == SigSpec(State::S0)) + invert_map[assign_map(cell->getPort("\\Y"))] = assign_map(cell->getPort("\\S")); if (ct_combinational.cell_known(cell->type)) for (auto &conn : cell->connections()) { RTLIL::SigSpec sig = assign_map(conn.second); |