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| author | Clifford Wolf <clifford@clifford.at> | 2014-01-17 16:42:40 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-01-17 16:42:40 +0100 |
| commit | 2e370d5a2f364a469f11a2dc6f4217a9e9880a1c (patch) | |
| tree | 0b0d823ab22dfdb0851f7d5d6e1651a4bc4cf36e /passes/opt | |
| parent | 651ce67d979d355c53e9bf17b91b22368adca072 (diff) | |
| download | yosys-2e370d5a2f364a469f11a2dc6f4217a9e9880a1c.tar.gz yosys-2e370d5a2f364a469f11a2dc6f4217a9e9880a1c.tar.bz2 yosys-2e370d5a2f364a469f11a2dc6f4217a9e9880a1c.zip | |
Added support for $adff with undef data inputs to opt_rmdff
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_rmdff.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index a84bf4376..9ce98004e 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -92,6 +92,12 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) } } + if (sig_d.is_fully_undef() && sig_d.width == int(val_rv.bits.size())) { + RTLIL::SigSig conn(sig_q, val_rv); + mod->connections.push_back(conn); + goto delete_dff; + } + if (sig_d.is_fully_const() && sig_r.width == 0) { RTLIL::SigSig conn(sig_q, sig_d); mod->connections.push_back(conn); |