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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-17 15:07:16 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-17 15:07:16 +0200 |
| commit | 2a78a1fd00fe66972885117efb1ac6a8b095f061 (patch) | |
| tree | 552cff1002a6941b56b7c3a3df5022d6ed049846 /passes/opt | |
| parent | ae5d8dc939678c85ba6dea78fdcfa133ddea0b92 (diff) | |
| parent | 27d59dc0550432458d4bd636081a7b9f4b4411fe (diff) | |
| download | yosys-2a78a1fd00fe66972885117efb1ac6a8b095f061.tar.gz yosys-2a78a1fd00fe66972885117efb1ac6a8b095f061.tar.bz2 yosys-2a78a1fd00fe66972885117efb1ac6a8b095f061.zip | |
Merge pull request #1283 from YosysHQ/clifford/fix1255
Fix various NDEBUG compiler warnings
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_expr.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index f7469853b..858b3560c 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -117,7 +117,8 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) } } -void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, std::string info, IdString out_port, RTLIL::SigSpec out_val) +void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, + const std::string &info YS_ATTRIBUTE(unused), IdString out_port, RTLIL::SigSpec out_val) { RTLIL::SigSpec Y = cell->getPort(out_port); out_val.extend_u0(Y.size(), false); |