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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-26 18:47:39 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-26 18:47:39 +0100 |
| commit | 1f1deda888ea32ade2478fca9fcb510ada477606 (patch) | |
| tree | bf21e5e60e970745af2d4652addfbe383f6b4187 /passes/opt | |
| parent | b005eedf369bc60ce5f7cba9a0db4694f22a360f (diff) | |
| download | yosys-1f1deda888ea32ade2478fca9fcb510ada477606.tar.gz yosys-1f1deda888ea32ade2478fca9fcb510ada477606.tar.bz2 yosys-1f1deda888ea32ade2478fca9fcb510ada477606.zip | |
Added non-std verilog assume() statement
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_clean.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index e9f653e5f..9d2a262a1 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -47,7 +47,7 @@ void rmunused_module_cells(Module *module, bool verbose) if (bit.wire != nullptr) wire2driver[bit].insert(cell); } - if (cell->type.in("$memwr", "$meminit", "$assert") || cell->has_keep_attr()) + if (cell->type.in("$memwr", "$meminit", "$assert", "$assume") || cell->has_keep_attr()) queue.insert(cell); else unused.insert(cell); |