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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-11 23:25:46 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-08-13 13:29:03 +0200 |
| commit | 0c5db07cd6cc3c19b926da21a46599f97592b20f (patch) | |
| tree | 7f9e731067e7bc75524837b04ab245e3300ee18b /passes/opt | |
| parent | c851dc13108021834533094a8a3236da6d9e0161 (diff) | |
| download | yosys-0c5db07cd6cc3c19b926da21a46599f97592b20f.tar.gz yosys-0c5db07cd6cc3c19b926da21a46599f97592b20f.tar.bz2 yosys-0c5db07cd6cc3c19b926da21a46599f97592b20f.zip | |
Fix various NDEBUG compiler warnings, closes #1255
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_expr.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index b2dc9a448..1512cea1b 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -117,7 +117,8 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) } } -void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val) +void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, + const std::string &info YS_ATTRIBUTE(unused), IdString out_port, RTLIL::SigSpec out_val) { RTLIL::SigSpec Y = cell->getPort(out_port); out_val.extend_u0(Y.size(), false); |