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| author | whitequark <whitequark@whitequark.org> | 2019-01-02 09:36:32 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-01-02 09:36:32 +0000 |
| commit | 06143ab33f4064677586be2a2b0d763f0818e856 (patch) | |
| tree | 693df3871bc11c1ed222bed63d0d52e6fe9bab97 /passes/opt | |
| parent | f7363ac5086ccb8bdb97dcdbfed890c54e1ed153 (diff) | |
| download | yosys-06143ab33f4064677586be2a2b0d763f0818e856.tar.gz yosys-06143ab33f4064677586be2a2b0d763f0818e856.tar.bz2 yosys-06143ab33f4064677586be2a2b0d763f0818e856.zip | |
opt_lut: use a worklist, and revisit cells affected by elimination.
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_lut.cc | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 8c564b0ed..a79a9a2da 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -189,7 +189,8 @@ struct OptLutWorker log("\n"); log("Eliminating LUTs.\n"); - for (auto lut : luts) + pool<RTLIL::Cell*> worklist = luts; + while (worklist.size()) { if (limit == 0) { @@ -197,6 +198,7 @@ struct OptLutWorker break; } + auto lut = worklist.pop(); SigSpec lut_input = sigmap(lut->getPort("\\A")); pool<int> &lut_dlogic_inputs = luts_dlogic_inputs[lut]; @@ -262,8 +264,13 @@ struct OptLutWorker else { SigSpec lut_output = lut->getPort("\\Y"); - module->connect(lut_output, value); + for (auto &port : index.query_ports(lut_output)) + { + if (port.cell != lut && luts.count(port.cell)) + worklist.insert(port.cell); + } + module->connect(lut_output, value); module->remove(lut); luts.erase(lut); luts_arity.erase(lut); @@ -280,7 +287,7 @@ struct OptLutWorker log("\n"); log("Combining LUTs.\n"); - pool<RTLIL::Cell*> worklist = luts; + worklist = luts; while (worklist.size()) { if (limit == 0) |