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author | Clifford Wolf <clifford@clifford.at> | 2014-10-10 16:59:44 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-10-10 17:07:24 +0200 |
commit | 4569a747f8af3880e23408eb93323afc8088b78b (patch) | |
tree | 81dcea51020173cd4951e8649f8bd8305e7c2591 /passes/opt/wreduce.cc | |
parent | c7f5aab625bb90e766c1852592fdf42c951716c0 (diff) | |
download | yosys-4569a747f8af3880e23408eb93323afc8088b78b.tar.gz yosys-4569a747f8af3880e23408eb93323afc8088b78b.tar.bz2 yosys-4569a747f8af3880e23408eb93323afc8088b78b.zip |
Renamed SIZE() to GetSize() because of name collision on Win32
Diffstat (limited to 'passes/opt/wreduce.cc')
-rw-r--r-- | passes/opt/wreduce.cc | 84 |
1 files changed, 42 insertions, 42 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 58a6d1b0d..89b1f8856 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -65,20 +65,20 @@ struct WreduceWorker SigSpec sig_y = mi.sigmap(cell->getPort("\\Y")); std::vector<SigBit> bits_removed; - for (int i = SIZE(sig_y)-1; i >= 0; i--) + for (int i = GetSize(sig_y)-1; i >= 0; i--) { auto info = mi.query(sig_y[i]); - if (!info->is_output && SIZE(info->ports) <= 1) { + if (!info->is_output && GetSize(info->ports) <= 1) { bits_removed.push_back(Sx); continue; } SigBit ref = sig_a[i]; - for (int k = 0; k < SIZE(sig_s); k++) { - if (ref != Sx && sig_b[k*SIZE(sig_a) + i] != Sx && ref != sig_b[k*SIZE(sig_a) + i]) + for (int k = 0; k < GetSize(sig_s); k++) { + if (ref != Sx && sig_b[k*GetSize(sig_a) + i] != Sx && ref != sig_b[k*GetSize(sig_a) + i]) goto no_match_ab; - if (sig_b[k*SIZE(sig_a) + i] != Sx) - ref = sig_b[k*SIZE(sig_a) + i]; + if (sig_b[k*GetSize(sig_a) + i] != Sx) + ref = sig_b[k*GetSize(sig_a) + i]; } if (0) no_match_ab: @@ -90,10 +90,10 @@ struct WreduceWorker return; SigSpec sig_removed; - for (int i = SIZE(bits_removed)-1; i >= 0; i--) + for (int i = GetSize(bits_removed)-1; i >= 0; i--) sig_removed.append_bit(bits_removed[i]); - if (SIZE(bits_removed) == SIZE(sig_y)) { + if (GetSize(bits_removed) == GetSize(sig_y)) { log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); module->connect(sig_y, sig_removed); module->remove(cell); @@ -101,10 +101,10 @@ struct WreduceWorker } log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n", - SIZE(sig_removed), SIZE(sig_y), log_id(module), log_id(cell), log_id(cell->type)); + GetSize(sig_removed), GetSize(sig_y), log_id(module), log_id(cell), log_id(cell->type)); - int n_removed = SIZE(sig_removed); - int n_kept = SIZE(sig_y) - SIZE(sig_removed); + int n_removed = GetSize(sig_removed); + int n_kept = GetSize(sig_y) - GetSize(sig_removed); SigSpec new_work_queue_bits; new_work_queue_bits.append(sig_a.extract(n_kept, n_removed)); @@ -114,9 +114,9 @@ struct WreduceWorker SigSpec new_sig_y = sig_y.extract(0, n_kept); SigSpec new_sig_b; - for (int k = 0; k < SIZE(sig_s); k++) { - new_sig_b.append(sig_b.extract(k*SIZE(sig_a), n_kept)); - new_work_queue_bits.append(sig_b.extract(k*SIZE(sig_a) + n_kept, n_removed)); + for (int k = 0; k < GetSize(sig_s); k++) { + new_sig_b.append(sig_b.extract(k*GetSize(sig_a), n_kept)); + new_work_queue_bits.append(sig_b.extract(k*GetSize(sig_a) + n_kept, n_removed)); } for (auto bit : new_work_queue_bits) @@ -139,24 +139,24 @@ struct WreduceWorker port_signed = false; int bits_removed = 0; - if (SIZE(sig) > max_port_size) { - bits_removed = SIZE(sig) - max_port_size; + if (GetSize(sig) > max_port_size) { + bits_removed = GetSize(sig) - max_port_size; for (auto bit : sig.extract(max_port_size, bits_removed)) work_queue_bits.insert(bit); sig = sig.extract(0, max_port_size); } if (port_signed) { - while (SIZE(sig) > 1 && sig[SIZE(sig)-1] == sig[SIZE(sig)-2]) - work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++; + while (GetSize(sig) > 1 && sig[GetSize(sig)-1] == sig[GetSize(sig)-2]) + work_queue_bits.insert(sig[GetSize(sig)-1]), sig.remove(GetSize(sig)-1), bits_removed++; } else { - while (SIZE(sig) > 1 && sig[SIZE(sig)-1] == S0) - work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++; + while (GetSize(sig) > 1 && sig[GetSize(sig)-1] == S0) + work_queue_bits.insert(sig[GetSize(sig)-1]), sig.remove(GetSize(sig)-1), bits_removed++; } if (bits_removed) { log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n", - bits_removed, SIZE(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type)); + bits_removed, GetSize(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type)); cell->setPort(stringf("\\%c", port), sig); did_something = true; } @@ -175,12 +175,12 @@ struct WreduceWorker // Reduce size of ports A and B based on constant input bits and size of output port - int max_port_a_size = cell->hasPort("\\A") ? SIZE(cell->getPort("\\A")) : -1; - int max_port_b_size = cell->hasPort("\\B") ? SIZE(cell->getPort("\\B")) : -1; + int max_port_a_size = cell->hasPort("\\A") ? GetSize(cell->getPort("\\A")) : -1; + int max_port_b_size = cell->hasPort("\\B") ? GetSize(cell->getPort("\\B")) : -1; if (cell->type.in("$not", "$pos", "$neg", "$and", "$or", "$xor", "$add", "$sub")) { - max_port_a_size = std::min(max_port_a_size, SIZE(cell->getPort("\\Y"))); - max_port_b_size = std::min(max_port_b_size, SIZE(cell->getPort("\\Y"))); + max_port_a_size = std::min(max_port_a_size, GetSize(cell->getPort("\\Y"))); + max_port_b_size = std::min(max_port_b_size, GetSize(cell->getPort("\\Y"))); } bool port_a_signed = false; @@ -201,14 +201,14 @@ struct WreduceWorker if (port_a_signed && cell->type == "$shr") { // do not reduce size of output on $shr cells with signed A inputs } else { - while (SIZE(sig) > 0) + while (GetSize(sig) > 0) { - auto info = mi.query(sig[SIZE(sig)-1]); + auto info = mi.query(sig[GetSize(sig)-1]); - if (info->is_output || SIZE(info->ports) > 1) + if (info->is_output || GetSize(info->ports) > 1) break; - sig.remove(SIZE(sig)-1); + sig.remove(GetSize(sig)-1); bits_removed++; } } @@ -218,8 +218,8 @@ struct WreduceWorker bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); int a_size = 0, b_size = 0; - if (cell->hasPort("\\A")) a_size = SIZE(cell->getPort("\\A")); - if (cell->hasPort("\\B")) b_size = SIZE(cell->getPort("\\B")); + if (cell->hasPort("\\A")) a_size = GetSize(cell->getPort("\\A")); + if (cell->hasPort("\\B")) b_size = GetSize(cell->getPort("\\B")); int max_y_size = std::max(a_size, b_size); @@ -229,14 +229,14 @@ struct WreduceWorker if (cell->type == "$mul") max_y_size = a_size + b_size; - while (SIZE(sig) > 1 && SIZE(sig) > max_y_size) { - module->connect(sig[SIZE(sig)-1], is_signed ? sig[SIZE(sig)-2] : S0); - sig.remove(SIZE(sig)-1); + while (GetSize(sig) > 1 && GetSize(sig) > max_y_size) { + module->connect(sig[GetSize(sig)-1], is_signed ? sig[GetSize(sig)-2] : S0); + sig.remove(GetSize(sig)-1); bits_removed++; } } - if (SIZE(sig) == 0) { + if (GetSize(sig) == 0) { log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); module->remove(cell); return; @@ -244,7 +244,7 @@ struct WreduceWorker if (bits_removed) { log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n", - bits_removed, SIZE(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type)); + bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type)); cell->setPort("\\Y", sig); did_something = true; } @@ -288,19 +288,19 @@ struct WreduceWorker if (w->port_id > 0 || count_nontrivial_wire_attrs(w) > 0) continue; - for (int i = SIZE(w)-1; i >= 0; i--) { + for (int i = GetSize(w)-1; i >= 0; i--) { SigBit bit(w, i); auto info = mi.query(bit); - if (info && (info->is_input || info->is_output || SIZE(info->ports) > 0)) + if (info && (info->is_input || info->is_output || GetSize(info->ports) > 0)) break; unused_top_bits++; } - if (0 < unused_top_bits && unused_top_bits < SIZE(w)) { - log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, SIZE(w), log_id(module), log_id(w)); + if (0 < unused_top_bits && unused_top_bits < GetSize(w)) { + log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w)); Wire *nw = module->addWire(NEW_ID, w); - nw->width = SIZE(w) - unused_top_bits; - module->connect(nw, SigSpec(w).extract(0, SIZE(nw))); + nw->width = GetSize(w) - unused_top_bits; + module->connect(nw, SigSpec(w).extract(0, GetSize(nw))); module->swap_names(w, nw); } } |