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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-13 08:17:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-13 08:17:39 -0700 |
| commit | 432a09af80f7dcba9fd517a001e3a1954c99537e (patch) | |
| tree | 1adf4d0a7cdf929de445b000255dfa8ca23663a5 /passes/opt/wreduce.cc | |
| parent | b567f03c266b0c44d81a24dde2ed538f1db05d4e (diff) | |
| download | yosys-432a09af80f7dcba9fd517a001e3a1954c99537e.tar.gz yosys-432a09af80f7dcba9fd517a001e3a1954c99537e.tar.bz2 yosys-432a09af80f7dcba9fd517a001e3a1954c99537e.zip | |
kernel: SigSpec use more const& + overloads to prevent implicit SigSpec
Diffstat (limited to 'passes/opt/wreduce.cc')
| -rw-r--r-- | passes/opt/wreduce.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 04b882db9..b5451849d 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -98,7 +98,7 @@ struct WreduceWorker SigSpec sig_removed; for (int i = GetSize(bits_removed)-1; i >= 0; i--) - sig_removed.append_bit(bits_removed[i]); + sig_removed.append(bits_removed[i]); if (GetSize(bits_removed) == GetSize(sig_y)) { log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); |