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author | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 11:58:59 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 11:58:59 -0700 |
commit | 4cfef7897f4bac285853bf0f08ae366523ae76b4 (patch) | |
tree | 238a71ec6696966652211fb79bd52c3c8c97eee7 /passes/opt/opt_merge.cc | |
parent | 4486a98fd5928a4e3cdf9cd27c27b7dd821513bb (diff) | |
parent | eaf3c247729365cec776e147f380ce59f7dccd4d (diff) | |
download | yosys-4cfef7897f4bac285853bf0f08ae366523ae76b4.tar.gz yosys-4cfef7897f4bac285853bf0f08ae366523ae76b4.tar.bz2 yosys-4cfef7897f4bac285853bf0f08ae366523ae76b4.zip |
Merge branch 'xaig' into xc7mux
Diffstat (limited to 'passes/opt/opt_merge.cc')
-rw-r--r-- | passes/opt/opt_merge.cc | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index eedf88904..7567d4657 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -315,17 +315,17 @@ struct OptMergeWorker { if (sharemap.count(cell) > 0) { did_something = true; - log(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str()); + log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str()); for (auto &it : cell->connections()) { if (cell->output(it.first)) { RTLIL::SigSpec other_sig = sharemap[cell]->getPort(it.first); - log(" Redirecting output %s: %s = %s\n", it.first.c_str(), + log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(), log_signal(it.second), log_signal(other_sig)); module->connect(RTLIL::SigSig(it.second, other_sig)); assign_map.add(it.second, other_sig); } } - log(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str()); + log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str()); #ifdef USE_CELL_HASH_CACHE cell_hash_cache.erase(cell); #endif @@ -336,6 +336,8 @@ struct OptMergeWorker } } } + + log_suppressed(); } }; |