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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-22 11:57:39 +0200 |
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| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-22 11:57:39 +0200 |
| commit | 75032a565d22506ae7910bfa00e2b71558a30e26 (patch) | |
| tree | a5b50451ab320dad400a7913fd21f8d13fdb59a3 /passes/opt/opt_mem_widen.cc | |
| parent | 8fa2f3b26036499945c8a7b27d2972ebc1322e01 (diff) | |
| download | yosys-75032a565d22506ae7910bfa00e2b71558a30e26.tar.gz yosys-75032a565d22506ae7910bfa00e2b71558a30e26.tar.bz2 yosys-75032a565d22506ae7910bfa00e2b71558a30e26.zip | |
Set init state for all wires from FST and set past
Diffstat (limited to 'passes/opt/opt_mem_widen.cc')
0 files changed, 0 insertions, 0 deletions