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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 19:18:05 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 21:53:55 -0700 |
| commit | d3a212ff91de5e4f082f2c133becd4338661ac16 (patch) | |
| tree | b7595adfd15904f60788e7c01259a5fb38c82179 /passes/opt/opt_expr.cc | |
| parent | 7d8db1c0538552d1893849ff8c9c60b2025ec267 (diff) | |
| download | yosys-d3a212ff91de5e4f082f2c133becd4338661ac16.tar.gz yosys-d3a212ff91de5e4f082f2c133becd4338661ac16.tar.bz2 yosys-d3a212ff91de5e4f082f2c133becd4338661ac16.zip | |
opt_expr to trim A port of $shiftx if Y_WIDTH == 1
Diffstat (limited to 'passes/opt/opt_expr.cc')
| -rw-r--r-- | passes/opt/opt_expr.cc | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 858b3560c..b56ce252f 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -745,6 +745,23 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } + if (cell->type == ID($shiftx) && cell->getPort(ID::Y).size() == 1) { + SigSpec sig_a = assign_map(cell->getPort(ID::A)); + int width; + for (width = GetSize(sig_a); width > 1; width--) { + if (sig_a[width-1] != State::Sx) + break; + } + + if (width < GetSize(sig_a)) { + sig_a.remove(width, GetSize(sig_a)-width); + cell->setPort(ID::A, sig_a); + cell->setParam(ID(A_WIDTH), width); + did_something = true; + goto next_cell; + } + } + if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && cell->getPort(ID::Y).size() == 1 && invert_map.count(assign_map(cell->getPort(ID::A))) != 0) { cover_list("opt.opt_expr.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str()); |