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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-24 14:13:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-24 14:13:45 -0700 |
| commit | b5f38f834207fab3a563c55568c4543a3b5dcc1f (patch) | |
| tree | f373965166801c4a30b53d255d6635ddfd8c9471 /passes/opt/opt_expr.cc | |
| parent | ebd6fa945d4f0afa9a7507e791d13653571c8a63 (diff) | |
| download | yosys-b5f38f834207fab3a563c55568c4543a3b5dcc1f.tar.gz yosys-b5f38f834207fab3a563c55568c4543a3b5dcc1f.tar.bz2 yosys-b5f38f834207fab3a563c55568c4543a3b5dcc1f.zip | |
opt_expr: const_xnor replacement to pad Y with 1'b1
Diffstat (limited to 'passes/opt/opt_expr.cc')
| -rw-r--r-- | passes/opt/opt_expr.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 38dc09af5..d895fc691 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -575,7 +575,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (cell->type.in(ID($xnor), ID($_XNOR_))) { cover("opt.opt_expr.const_xnor"); // For consistency since simplemap does $xnor -> $_XOR_ + $_NOT_ - replace_cell(assign_map, module, cell, "const_xnor", ID::Y, RTLIL::State::S1); + int width = cell->getParam(ID::Y_WIDTH).as_int(); + replace_cell(assign_map, module, cell, "const_xnor", ID::Y, SigSpec(RTLIL::State::S1, width)); goto next_cell; } log_abort(); |