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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-08 11:12:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-08 11:12:43 -0700 |
| commit | 9694dc42dd8badde03a27072b294556cb77f5bb5 (patch) | |
| tree | 888528a8ffbb5c65f41073fddf8b3e478657ac06 /passes/opt/opt_expr.cc | |
| parent | 17f4e06247b608034f730efe6391fd5fe250bd79 (diff) | |
| download | yosys-9694dc42dd8badde03a27072b294556cb77f5bb5.tar.gz yosys-9694dc42dd8badde03a27072b294556cb77f5bb5.tar.bz2 yosys-9694dc42dd8badde03a27072b294556cb77f5bb5.zip | |
opt_expr: consume_x to require/imply !keepdc
Diffstat (limited to 'passes/opt/opt_expr.cc')
| -rw-r--r-- | passes/opt/opt_expr.cc | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 60221f32d..9a8bc0869 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -543,13 +543,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if (detect_const_and && (found_zero || found_inv || (!keepdc && found_undef && consume_x))) { + if (detect_const_and && (found_zero || found_inv || (found_undef && consume_x))) { cover("opt.opt_expr.const_and"); replace_cell(assign_map, module, cell, "const_and", ID::Y, RTLIL::State::S0); goto next_cell; } - if (detect_const_or && (found_one || found_inv || (!keepdc && found_undef && consume_x))) { + if (detect_const_or && (found_one || found_inv || (found_undef && consume_x))) { cover("opt.opt_expr.const_or"); replace_cell(assign_map, module, cell, "const_or", ID::Y, RTLIL::State::S1); goto next_cell; @@ -1149,7 +1149,7 @@ skip_fine_alu: goto next_cell; } - if (!keepdc && consume_x) + if (consume_x) { bool identity_wrt_a = false; bool identity_wrt_b = false; @@ -2041,11 +2041,12 @@ struct OptExprPass : public Pass { do { do { did_something = false; - replace_const_cells(design, module, false, mux_undef, mux_bool, do_fine, keepdc, clkinv); + replace_const_cells(design, module, false /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, clkinv); if (did_something) design->scratchpad_set_bool("opt.did_something", true); } while (did_something); - replace_const_cells(design, module, true, mux_undef, mux_bool, do_fine, keepdc, clkinv); + if (!keepdc) + replace_const_cells(design, module, true /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, clkinv); if (did_something) design->scratchpad_set_bool("opt.did_something", true); } while (did_something); |