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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-18 12:21:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-18 12:21:40 -0700 |
| commit | 7ad7f41bc555d7fc77a2201cdc485702505df637 (patch) | |
| tree | ca262dbd1d7e7e598228c3bf97898e5fac535b57 /passes/opt/opt_expr.cc | |
| parent | a0cc795e85541b0326b6d4396a726142f0d0f8bb (diff) | |
| download | yosys-7ad7f41bc555d7fc77a2201cdc485702505df637.tar.gz yosys-7ad7f41bc555d7fc77a2201cdc485702505df637.tar.bz2 yosys-7ad7f41bc555d7fc77a2201cdc485702505df637.zip | |
kernel: share a single CellTypes within a pass
Diffstat (limited to 'passes/opt/opt_expr.cc')
| -rw-r--r-- | passes/opt/opt_expr.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 4a2f170b8..c13184025 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -31,9 +31,8 @@ PRIVATE_NAMESPACE_BEGIN bool did_something; -void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) +void replace_undriven(RTLIL::Module *module, const CellTypes& ct) { - CellTypes ct(design); SigMap sigmap(module); SigPool driven_signals; SigPool used_signals; @@ -1737,13 +1736,14 @@ struct OptExprPass : public Pass { } extra_args(args, argidx, design); + CellTypes ct(design); for (auto module : design->selected_modules()) { log("Optimizing module %s.\n", log_id(module)); if (undriven) { did_something = false; - replace_undriven(design, module); + replace_undriven(module, ct); if (did_something) design->scratchpad_set_bool("opt.did_something", true); } |