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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 07:13:33 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-02 07:13:33 -0700 |
| commit | 37f42fe102e329793b884a47321423062eedfce7 (patch) | |
| tree | 42cca1494ce7d806e8a638fe56bc8acd13733a21 /passes/opt/opt_expr.cc | |
| parent | 347774945972dc71910a3e38c9ec678f74f97d03 (diff) | |
| parent | 348e8923148f1cc1bfb87bb71b7566d4bc111704 (diff) | |
| download | yosys-37f42fe102e329793b884a47321423062eedfce7.tar.gz yosys-37f42fe102e329793b884a47321423062eedfce7.tar.bz2 yosys-37f42fe102e329793b884a47321423062eedfce7.zip | |
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
kernel: speedup by using more pass-by-const-ref
Diffstat (limited to 'passes/opt/opt_expr.cc')
| -rw-r--r-- | passes/opt/opt_expr.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index a92643134..f9c5f68f2 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -192,11 +192,11 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ for (auto &it : grouped_bits[i]) { for (auto &bit : it.second) { - new_conn.first.append_bit(bit); - new_conn.second.append_bit(RTLIL::SigBit(new_y, new_a.size())); + new_conn.first.append(bit); + new_conn.second.append(RTLIL::SigBit(new_y, new_a.size())); } - new_a.append_bit(it.first.first); - new_b.append_bit(it.first.second); + new_a.append(it.first.first); + new_b.append(it.first.second); } if (cell->type.in(ID($and), ID($or)) && i == GRP_CONST_A) { |