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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-20 14:39:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-20 14:39:08 -0700 |
| commit | 0c0dc4ffc3c907fbe6973c925e9de07c2286cd6a (patch) | |
| tree | a62aae0ef229b7e14dcd760509d6d5b669b7db79 /passes/opt/opt_expr.cc | |
| parent | 6274f0b075abba2af9193e2245eacee5cc66e4c5 (diff) | |
| download | yosys-0c0dc4ffc3c907fbe6973c925e9de07c2286cd6a.tar.gz yosys-0c0dc4ffc3c907fbe6973c925e9de07c2286cd6a.tar.bz2 yosys-0c0dc4ffc3c907fbe6973c925e9de07c2286cd6a.zip | |
opt_expr: fix failing $xnor test
Diffstat (limited to 'passes/opt/opt_expr.cc')
| -rw-r--r-- | passes/opt/opt_expr.cc | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 4163c31f0..1a586711c 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -505,12 +505,27 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (sig_b == State::S0 || sig_b == State::S1) { if (cell->type.in(ID($xor), ID($_XOR_))) { cover("opt.opt_expr.xor_buffer"); - replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a); + SigSpec sig_y; + if (cell->type == ID($xor)) + sig_y = (sig_b == State::S1 ? module->Not(NEW_ID, sig_a).as_bit() : sig_a); + else if (cell->type == ID($_XOR_)) + sig_y = (sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a); + else log_abort(); + replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_y); goto next_cell; } if (cell->type.in(ID($xnor), ID($_XNOR_))) { cover("opt.opt_expr.xnor_buffer"); - replace_cell(assign_map, module, cell, "xnor_buffer", ID::Y, sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a)); + SigSpec sig_y; + if (cell->type == ID($xnor)) { + sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID, sig_a).as_bit()); + int width = cell->getParam(ID(Y_WIDTH)).as_int(); + sig_y.append(RTLIL::Const(State::S1, width-1)); + } + else if (cell->type == ID($_XNOR_)) + sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a)); + else log_abort(); + replace_cell(assign_map, module, cell, "xnor_buffer", ID::Y, sig_y); goto next_cell; } log_abort(); |