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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-06 11:46:10 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-05-06 11:46:10 +0200 |
| commit | c7f2e93024b7758a865254cfb350997645f663b2 (patch) | |
| tree | beceebda977448886bb910e1053083741c78da95 /passes/opt/opt_clean.cc | |
| parent | 87426f5a06b0cf9d1fe44efda65e3c048d89d322 (diff) | |
| parent | 70d0f389ad6e7e0ad762b62d3a626a4db5b23827 (diff) | |
| download | yosys-c7f2e93024b7758a865254cfb350997645f663b2.tar.gz yosys-c7f2e93024b7758a865254cfb350997645f663b2.tar.bz2 yosys-c7f2e93024b7758a865254cfb350997645f663b2.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify
Diffstat (limited to 'passes/opt/opt_clean.cc')
| -rw-r--r-- | passes/opt/opt_clean.cc | 32 |
1 files changed, 22 insertions, 10 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 2f7995071..c00ea06b2 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -242,6 +242,10 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos } } + SigPool raw_used_signals_noaliases; + for (auto &it : module->connections_) + raw_used_signals_noaliases.add(it.second); + module->connections_.clear(); SigPool used_signals; @@ -251,6 +255,7 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos for (auto &it2 : cell->connections_) { assign_map.apply(it2.second); used_signals.add(it2.second); + raw_used_signals_noaliases.add(it2.second); if (!ct_all.cell_output(cell->type, it2.first)) used_signals_nodrivers.add(it2.second); } @@ -277,23 +282,30 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos SigSpec s1 = SigSpec(wire), s2 = assign_map(s1); log_assert(GetSize(s1) == GetSize(s2)); + Const initval; + if (wire->attributes.count("\\init")) + initval = wire->attributes.at("\\init"); + if (GetSize(initval) != GetSize(wire)) + initval.bits.resize(GetSize(wire), State::Sx); + if (initval.is_fully_undef()) + wire->attributes.erase("\\init"); + bool maybe_del = false; - if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0 || wire->get_bool_attribute("\\keep") || wire->attributes.count("\\init")) { - if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep")) - maybe_del = true; + if (wire->port_id != 0 || wire->get_bool_attribute("\\keep") || !initval.is_fully_undef()) { + /* do not delete anything with "keep" or module ports or initialized wires */ + } else + if (!purge_mode && check_public_name(wire->name)) { + /* do not get rid of public names unless in purge mode */ } else { - if (!used_signals.check_any(s2)) + if (!raw_used_signals_noaliases.check_any(s1)) + maybe_del = true; + if (!used_signals_nodrivers.check_any(s2)) maybe_del = true; } if (maybe_del) { maybe_del_wires.push_back(wire); } else { - Const initval; - if (wire->attributes.count("\\init")) - initval = wire->attributes.at("\\init"); - if (GetSize(initval) != GetSize(wire)) - initval.bits.resize(GetSize(wire), State::Sx); RTLIL::SigSig new_conn; for (int i = 0; i < GetSize(s1); i++) if (s1[i] != s2[i]) { @@ -341,7 +353,7 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos int del_wires_count = 0; for (auto wire : maybe_del_wires) { SigSpec s1 = SigSpec(wire); - if (used_signals.check_any(s1)) { + if (used_signals_nodrivers.check_any(s1)) { SigSpec s2 = assign_map(s1); Const initval; if (wire->attributes.count("\\init")) |