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| author | Zachary Snow <zach@zachjs.com> | 2021-03-04 15:08:16 -0500 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2021-03-04 15:20:52 -0500 |
| commit | c18ddbcd822410095d28c4be1c3ac3c6358622d2 (patch) | |
| tree | 405d9312fc0b723f0af7b730bece916fde66fc1a /passes/opt/opt_clean.cc | |
| parent | 7d2097b00538fa366cc433b23c2c307db0e3a4be (diff) | |
| download | yosys-c18ddbcd822410095d28c4be1c3ac3c6358622d2.tar.gz yosys-c18ddbcd822410095d28c4be1c3ac3c6358622d2.tar.bz2 yosys-c18ddbcd822410095d28c4be1c3ac3c6358622d2.zip | |
verilog: impose limit on maximum expression width
Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.
Diffstat (limited to 'passes/opt/opt_clean.cc')
0 files changed, 0 insertions, 0 deletions